An interconnect in an integrated circuit (IC) distributes clock, regulatory and other signals as well as power or ground voltages to various components and circuits on a chip. The International Technology Roadmap for Semiconductors (ITRS) emphasizes the high speed transmission requirements on a chip as the driver for future interconnect development. Near term and long term interconnect requirements for microprocessors (MPs) and for dynamic random access memories (DRAMs) are outlined in the ITRS. Microprocessors require local, intermediate and global wiring solutions and present both material and processing difficulties. Susceptibility of common interconnect metals to electro-migration at high current densities (above 106 Amp/cm2) is a problem. Copper interconnect, introduced in 1998, is now routinely used, with minimum feature size down to 90 nm. However, electrical resistivity of copper increases with decreasing dimensions and is attributed to scattering at surfaces and at grain boundaries. These size effects are due to interface roughness and through use of small grain sizes, which are hard to overcome and cannot be avoided by simply cooling to lower the resistivity. With reference to processing, present interconnect technology relies upon successful development of three processes: dry etching to create trenches and vias; deposition to fill metal plugs; and planarization. The aspect ratio of contact apertures is now 12:1 and may reach 23:1 by the year 2016. Creating high aspect ratio apertures with straight walls and uniform diameters using dry etching is an extremely difficult task and is expected to become progressively more difficult with each succeeding generation. HBr etching of SiO2 for a 9:1 aspect ratio contact hole has been found to provide a 135 mm diameter at one end and a 70 nm diameter at the other end of the hole by Hwang, Meyyappan, Mathod and Ranade, Jour. Vac. Sci. Technol., vol. 20B (2002) 2199. Aspect ratio-dependent etching becomes a serious problem with each new decrease in feature size. Plasma damage and cleaning of high aspect ratio features also pose concerns. Void-free filling of a high aspect ratio aperture is another concern.
Well known properties of copper such as high current carrying capacity and material robustness, would make copper ideally suited for use in electrical interconnects, if the fabrication problems could be resolved.
An electrical interconnect in an integrated circuit (IC) chip uses some form of metallization. Interconnect technology that, as presently practiced, depends upon at least processing three steps: (1) creating a trench of the right size in an insulator material, such as SiO2 or another dielectric, using a procedure such as dry etching; (2) filling the trench with an appropriate interconnect metal material; and (3) chemical mechanical polishing (CMP) to obtain a planar surface. Creating deep, narrow trenches with flat side walls (step (1)) stretches the capabilities of dry etching equipment and processes. Cleaning a trench after its creation is also a problem, in part because of the shrinking width of the trench. Filling a deep, narrow trench with an interconnect metal, in a manner that does not create voids, is also becoming a problem. The combination of these difficulties makes the interconnect technology a critical technical area, according to the ITRS, which requires substantial innovation in material, design and associated processes.
Transistor node size is being reduced with each successive generation including the source, drain and gate contacts. Provision of good Ohmic contacts for these nodes are crucial for fast, reliable device performance.
What is needed is an approach that provides small diameter electrical interconnects, with a metal-like material such as copper or a suitable alloy, that does not suffer from the difficulties of trench creation and trench filling discussed in the preceding. Preferably, the approach should (1) provide reasonably uniform diameter nanowires with aspect ratios up to or higher than 100:1, (2) allow use of a variety of gap-filling insulating materials, (3) allow use of current densities of 106 Amps/cm2 and higher without serious electro-migration problems, (4) show substantially no degradation at moderate or high current densities over long time intervals, and (5) generally meet DRAM and microprocessor requirements. Preferably, the approach should be flexible and allow interconnects with a range of small diameters to be created and allows some flexibility in the choice of composition for the interconnect material.